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2010 Microchip Technology Inc.
DS41303G-page 35
PIC18F2XK20/4XK20
2.6
PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from the crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator. There are
three conditions when the PLL can be used:
When the primary clock is HSPLL
When the primary clock is HFINTOSC and the
selected frequency is 16 MHz
When the primary clock is HFINTOSC and the
selected frequency is 8 MHz
2.6.1
HSPLL OSCILLATOR MODE
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 16 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 64 MHz. The PLLEN bit of the
OSCTUNE register is active only when the HFINTOSC
is the primary clock and is not available in HSPLL oscil-
lator mode.
The PLL is only available to the primary oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (= 0110).
FIGURE 2-6:
PLL BLOCK DIAGRAM
(HS MODE)
2.6.2
PLL IN HFINTOSC MODES
The 4x frequency multiplier can be used with the inter-
nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 64 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The PLLEN control bit of the OSCTUNE
register is used to enable or disable the PLL operation
when the HFINTOSC is used.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC<3:0> = 1001 or 1000). Additionally, the
PLL will only function when the selected output fre-
quency is either 8 MHz or 16 MHz (OSCCON<6:4> =
111
or 110). If both of these conditions are not met, the
PLL is disabled.
The PLLEN control bit is only functional in those inter-
nal oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.
MU
X
VCO
Loop
Filter
Crystal
Osc
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS Oscillator Enable
4
(from Configuration Register 1H)
HS Mode
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